Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
GEMM (General Matrix Multiplication) is a fundamental operation in deep learning (DL), serving as the key computing kernel for neural network layers, such as convolutional and fully connected layers. As the deployment of DL models expands beyond high-performance computing to resource-constrained embedded systems, there is a growing demand for efficient GEMM implementations that can meet strict power budgets and real-time processing requirements. This paper introduces a dual-issue in-order RISC-V core with an inpipeline GEMM accelerator based on the VeeR EH1 core [13], eliminating control signals and data transfer overhead inherent to coprocessors and standalone accelerators. By integrating GEMM execution directly into the pipeline, the design leverages core utilization and enables compiler-time preloading of operands, streamlining memory access and reducing dynamic branching, thereby minimizing branch mispredictions. Further, pipelined load/store operations mitigate memory access stalls and cache misses, thereby enhancing the pipeline throughput. Speedup, measured using Verilator simulation, demonstrates an average of ∼ 5 × over the reference VeeR EH1 baseline core. By integrating GEMM acceleration within the pipeline, this work bridges the gap between domain-specific accelerators and general-purpose cores, delivering scalable computing performance.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | Proceedings - 35th International Conference on Field-Programmable Logic and Applications, FPL 2025 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers (IEEE) |
| Seiten | 273-281 |
| Seitenumfang | 9 |
| ISBN (elektronisch) | 979-8-3315-9153-3 |
| ISBN (Print) | 979-8-3315-9154-0 |
| Publikationsstatus | Veröffentlicht - März 2026 |
| Peer-Review-Status | Ja |
Publikationsreihe
| Reihe | International Conference on Field Programmable Logic and Applications (FPL) |
|---|---|
| ISSN | 1946-147X |
Konferenz
| Titel | 35th International Conference on Field-Programmable Logic and Applications |
|---|---|
| Kurztitel | FPL 2025 |
| Veranstaltungsnummer | 35 |
| Dauer | 1 - 5 September 2025 |
| Webseite | |
| Ort | CORPUS Congress Centre |
| Stadt | Leiden |
| Land | Niederlande |
Externe IDs
| ORCID | /0000-0003-2571-8441/work/223382084 |
|---|
Schlagworte
ASJC Scopus Sachgebiete
- Artificial intelligence - dual-issue pipeline, embedded systems, FPGAs, GEMM acceleration, RISC-V
- Computernetzwerke und -kommunikation - dual-issue pipeline, embedded systems, FPGAs, GEMM acceleration, RISC-V
- Hardware und Architektur - dual-issue pipeline, embedded systems, FPGAs, GEMM acceleration, RISC-V
- Angewandte Informatik - dual-issue pipeline, embedded systems, FPGAs, GEMM acceleration, RISC-V
- Software - dual-issue pipeline, embedded systems, FPGAs, GEMM acceleration, RISC-V
Schlagwörter
- dual-issue pipeline, embedded systems, FPGAs, GEMM acceleration, RISC-V