Signal processing applications are widely used in edge domains such as industrial IoT and smart healthcare. Since edge devices are typically battery-powered, they face strict power constraints. At the same time, the nature of the applications running on these devices is constantly evolving. Therefore, a flexible and energy-efficient architecture is essential to acceler-ate these applications. Reconfigurable architectures provide the flexibility required by edge applications. In particular, Coarse-Grained Reconfigurable Architectures (CGRAs) demonstrate higher energy efficiency over Field-Programmable Gate Arrays (FPGAs) owing to their word-level reconfigurability. This work investigates several techniques to further enhance the energy efficiency of reconfigurable accelerators, specifically CGRAs and systolic arrays, with emphasis on heterogeneous CGRA design and near-threshold operation.