Recent research has shown that current density-based models for electromigration (EM) lack precision and should be replaced by physics-based hydrostatic stress simulation. While this new approach is widely accepted in the research community, it has not yet found its way into mainstream IC design flows. This paper aims at bringing state-of-the-art stress-based EM modeling into practical IC design. This is achieved by first examining the reasons that prevent the use of stress modeling in today's verification flows, and then proposing solutions that address these obstacles, such as extracting the necessary technology information from standard IC lifetime testing. The proposed stress modeling approach is used to calculate the EM lifetime for example structures based on equivalent RC circuits, using common IC design tools. Finally, the presented approach is further verified by implementing reservoirs for extending interconnect lifetime.