Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors

Publikation: Beitrag zu KonferenzenPaperBeigetragenBegutachtung

Abstract

Current Intel processors implement a variety of power saving features like frequency scaling and idle states. These mechanisms limit the power draw and thereby decrease the thermal dissipation of the processors. However, they also have an impact on the achievable performance. The various mechanisms significantly differ regarding the amount of power savings, the latency of mode changes, and the associated overhead. In this paper, we describe and closely examine the so-called software controlled clock modulation mechanism for different processor generations. We present results that imply that the available documentation is not always correct and describe when this feature can be used to improve energy efficiency. We additionally compare it against the more popular feature of dynamic voltage and frequency scaling and develop a model to decide which feature should be used to optimize inter-process synchronizations on Intel Haswell-EP processors.

Details

OriginalspracheEnglisch
Seiten69-76
Seitenumfang8
PublikationsstatusVeröffentlicht - 2016
Peer-Review-StatusJa

Workshop

Titel4th International Workshop on Energy Efficient Supercomputing
KurztitelE2SC 2016
Veranstaltungsnummer4
Beschreibungheld in conjunction with SC16: The International Conference for High Performance Computing, Networking, Storage and Analysis
Dauer14 November 2016
OrtSalt Palace Convention Center
StadtSalt Lake City
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0002-8491-770X/work/141543275
ORCID /0009-0003-0666-4166/work/151475568
ORCID /0000-0002-5437-3887/work/154740497

Schlagworte

Ziele für nachhaltige Entwicklung

Schlagwörter

  • dynamic voltage scaling, microprocessors, systems modeling, performance analysis