Shiftsreduce: Minimizing shifts in racetrack memory 4.0

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Beitragende

Abstract

Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%.

Details

OriginalspracheEnglisch
Aufsatznummer56
FachzeitschriftACM transactions on architecture and code optimization
Jahrgang16
Ausgabenummer4
PublikationsstatusVeröffentlicht - Dez. 2019
Peer-Review-StatusJa

Externe IDs

ORCID /0000-0002-5007-445X/work/141545534

Schlagworte

Forschungsprofillinien der TU Dresden

Ziele für nachhaltige Entwicklung

Schlagwörter

  • Compiler optimization, Data placement, Domain wall memory, Heuristics, Integer linear programming, Racetrack memory, Shifts minimization

Bibliotheksschlagworte