This study presents a significant advance in the field of self-organized synchronization using mutually delay-coupled phase-locked loops (PLLs) operating at 60GHz. To confirm mutual synchronization, an integrated PLL architecture was designed in a 130nm SiGe BiCMOS technology. Two nodes of these PLLs are mutually delay-coupled, and the effects of different division factors and time delays between the nodes are evaluated and compared with analytical predictions. An analysis of the accuracy of self-organized mutual synchronization is also performed. The study reveals that the division factor of the PLL significantly affects mutual synchronization behavior. The timing error has a standard deviation of 86.22ps, while the peak-to- peak error is 590.95ps.