In this work we present a new static circuit topology for sub-threshold (sub-VT) digital design. Proposed topology is derived from SCMOS but modifications are done to introduce new adjustable parameters to provide about 4X more control on the delay and active-mode leakage of gates. Proposed gates have full-swing input and output signaling but when the internal NMOS/PMOS transistors are off, they have negative Vgs/Vsg bias, respectively. By controlling the amount of these reverse biases, we can compensate process and temperature variations. Proposed method can be applied to any device or technology node and has 20% area and delay overheads.