This paper presents the study of the trade-off between retimer bias current and timing margin in a full-rate CDR operating at two different data rates. Using a dual-rate, referenceless CDR implemented in 130nm SiGe BiCMOS, we investigate whether power can be saved in the retimer by scaling bias currents at lower data rates and quantify the associated cost in timing margin. The CDR employs a phase-locked-loop architecture with a bang-bang phase detector, a dual-band LC voltage-controlled oscillator using switched inductors for dual-rate operation and a retimer. This architecture allows the relationship between retimer bias current, timing margin, and power consumption to be investigated at different data rates. The bias current of the emitter-followers (EFs)–which provide level shifting and buffering in high-speed circuits–can be scaled with data rate, offering a general path to power reduction. The key challenge is to understand how much timing margin must be sacrificed when this bias is reduced in the retimer. Transient simulations and recovered data bathtub curve measurements are used to quantify the effect of this bias scaling on the recovered data eye opening and the timing margin. The results show a clear dependence on data rate, i.e., at 25Gbps the timing margin degrades rapidly with reduced bias current, while at 11Gbps it decreases gradually. This enables 44% reduction of the EF bias current from 2.7mA down to 1.5mA at the lower data rate with minimal margin degradation. These results validate the EF stage as an effective knob for power-timing trade-offs in multi-rate CDRs, and provide the first quantitative characterization of how this trade-off depends on data rate.