Silicon nanowires are currently being considered as possible candidates for Beyond-CMOS electronic applications. One attractive nanowire transistor concept is the Schottky junction FET where the source and drain regions are metallic. The most appropriate device geometry to couple the gate potential to the junctions is an axial metal / semiconductor / metal nanowire heterostructure. Here, NiSi₂ / Si / NiSi₂ nanowire heterostructures are fabricated and used as the core of our transistors. Characteristic advantages of these structures are the abrupt and homogeneous Schottky interfaces formed. In contrast to most Schottky FETs the clear definition of the junction area, as given by the nanowire cross-section has the prospect of reducing device to device variability. Back gated devices show current densities over 1 × 10⁶ A/cm² at IV bias. The scaled peak trans-conductance amounts to 130 μS/μm. The effect of diameter scaling of untreated nanowires is shown, showing unipolar p-type behavior for thin wires and ambipolar behavior for wires with increasing diameters. This effect is eliminated by proper treatment in forming gas and is attributed to the large sensitivity of the Schottky junctions to surrounding oxide charges.