In-memory computing is a promising approach for realizing energy-efficient computing engines for artificial intelligence hardware. Among various memory technologies, ferroelectric devices stand out as strong candidates for in-memory computing due to their nonvolatile nature, low energy consumption, and multi-bit capability. For large-scale ferroelectric device-based memory circuit design, accurate and efficient compact models are essential. However, modeling these devices remains challenging due to their complex switching dynamics and device variability. This work presents a compact model based on the Nucleation-Limited Switching theory for simulating ferroelectric capacitors and ferroelectric tunnel junctions. After incorporating flexible mathematical models for current, these models accurately capture the switching kinetics and I-V characteristics of discrete devices. Moreover, their simple mathematical structure ensures high stability and robustness in memory circuit simulations, which is verified in an FTJ-based 32×32 crossbar array.