The ability of the reconfigurable systems to provide flexible and high-performance hardware has contributed to the fact that their popularity and multifaceted usage increased enormously in recent years [1] . They are occupying a central position in our modern complex systems. The development of Field Programmable Gate Arrays (FPGA) has taken hardware flexibility, in general, one step further. In recent years, many approaches have been developed that exploit dynamic reconfigurability of FPGAs, especially Xilinx FPGAs. Dynamic partial reconfiguration (DPR) and especially relocation are well-established and promising techniques in this area. In this context, the use of partial reconfiguration to add the adaptability feature to the design makes system design even more complex [2] . Therefore, solutions that help to reduce time and design efforts are needed. One of these solutions is bitstream manipulation. This approach leads to the user being able to perform modifications at runtime, thus reducing design time significantly.