Lossless 1.6 Mbits/s FPGA-based Real-Time Data Transmission System for Converse ME Sensors

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Andrey Morales-Zamora - , Bilkent University (Autor:in)
  • Johan Arbustini - , Christian-Albrechts-Universität zu Kiel (CAU) (Autor:in)
  • Pablo Mendoza-Ponce - , Bilkent University (Autor:in)
  • Eric Elzenheimer - , Christian-Albrechts-Universität zu Kiel (CAU) (Autor:in)
  • Cristopher McGuinness-Rodriguez - , Bilkent University (Autor:in)
  • Michael Höft - , Christian-Albrechts-Universität zu Kiel (CAU) (Autor:in)
  • Robert Rieger - , Christian-Albrechts-Universität zu Kiel (CAU) (Autor:in)
  • Andreas Bahr - , Professur für Biomedizinische Elektronik (Autor:in)

Abstract

This paper presents an FPGA-based system designed to address the need for a real-time (bio-)medical data transmission system for Converse-Magnetoelectric (C-ME) sensors, where its output signal behaves as a Double-Sideband Amplitude-Modulation with Carrier. The primary objective of this work is to ensure data integrity and efficient data management for continuous data capture and lossless transmission, even during performance-intensive periods. The proposed system assumes an optimized preamplification stage for basic sensor readout, an Analog-to-Digital conversion process, and a digital Demodulator, which reconstructs the to-be-measured magnetic signal at baseband frequency with a resolution of 32 bits, at down-converted sampling frequency of 50 kSa/s. The FPGA manages the data from the Demodulator to ensure real-time transmission via an SPI-to-USB (S2U) board interface. The register-transfer-level components were designed in SystemVerilog and implemented on an Artix-7 FPGA. The system incorporates a proposed rotating SPI FIFO module (a three-buffering technique within a half-duplex configuration). This configuration ensures continuous and lossless operation data in batches of 1000 Bytes, compatible with the receiver buffer of the S2U interface. System integration verification was performed using the Integrated Logic Analyzer IP-core, while a Python script controlled the SPI interface for initialization, configuration, and data integrity verification. The results demonstrate that our system achieves 0 % data loss while maintaining 1.6 Mbits/s (32 bits at 50 kSa/s). The low resource utilization on the FPGA leaves room for additional functionalities, providing a reliable and scalable system for real-time data transmission. Future research on system performance optimization could potentially enable the integration of advanced algorithms for C-ME sensor’s multiarray configurations, enabling data analysis and integration with other platforms.

Details

OriginalspracheEnglisch
Titel2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII)
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
Seitenumfang6
ISBN (elektronisch)979-8-3503-6672-3
ISBN (Print)979-8-3503-6673-0
PublikationsstatusVeröffentlicht - 29 Nov. 2024
Peer-Review-StatusJa

Konferenz

Titel2024 IEEE 42nd Central America and Panama Convention
KurztitelCONCAPAN XLII
Veranstaltungsnummer42
Dauer27 - 29 November 2024
Webseite
OrtHotel Crowne Plaza San José, La Sabana
StadtSan José
LandCosta Rica

Externe IDs

ORCID /0000-0001-8012-6794/work/184006559
Scopus 105005868357