This paper presents a detailed study of the jitter characteristics of both the recovered clock and recovered data in a referenceless clock and data recovery (CDR) circuit. The CDR is implemented in 130-nm SiGe BiCMOS technology, operates at 27.5 Gbps, and employs a phase-locked loop (PLL) architecture based on a bang-bang phase detector (BBPD). The work investigates two key aspects: the effect of static phase offsets in BBPDs on recovered data jitter, and the effect of varying the loop filter cutoff frequency fc on the recovered clock jitter and the CDR's jitter tolerance. Measurements show that biasing the BBPD at currents that minimize static phase offset also minimizes the peak-to-peak jitter of the recovered data. Simulations and measurements further show that tuning fc leads to a trade-off in the CDR's jitter performance, i.e., lowering fc reduces recovered clock jitter but degrades tolerance to high-frequency input jitter, while increasing fc improves tolerance at the expense of increased clock jitter. This offers an improved understanding of the jitter behavior in high-speed referenceless CDRs and helps with optimal loop filter design that balances clock quality and data recovery.