The influence of ferroelectric anneals on CMOS characteristics was evaluated. Experimental data for sheet resistances and CMOS device parameters (thin oxide transistor and parasitic FOX-transistor) were collected for different ferroelectric annealing conditions (90 min, 650°-800°C). By calibrating deactivation parameters and implementing them into simulation tools the experimentally observed sheet resistance behaviour was quantitatively confirmed by simulation. Additionally extrapolations to more arbitrary annealing conditions were possible. For FOX-devices an increase of the positive interface charge, which is critical for the n-channel FOX-device, was observed. For the thin oxide devices only a marginal influence on performance is seen.