This article presents a fractional-N phase-locked loop (PLL) for the use in frequency-modulated continuous wave (FMCW) radar systems. The presented design supports division ratios from 59 to 4092 with a maximum input frequency of 7GHz, covering the 2.39GHz to 3.28GHz and 4.79GHz to 6.55GHz bands using a dual-band voltage-controlled oscillator (VCO) with a frequency resolution of 0.6Hz. This corresponds to a large relative bandwidth of more than 31%. Reference spur levels are lower than -65 dBc while phase noise is at -103 dBc/Hz at 1MHz offset frequency. A key feature for radar applications is the automatic chirp waveform generation. The complete circuit including VCO consumes less than 122mW and is implemented using an IBM 180 nm SiGe BiCMOS process.