Data-driven applications require high-bandwidth communication between processing elements (PEs) and on-chip memory to achieve efficient parallel computation. Tightly coupled data memory (TCDM) architectures, which feature multiple memory banks and low access latency, are commonly used to meet these demands. Studies have shown that bank prediction can reduce both access latency and energy usage. While prior work has demonstrated the potential of bank prediction to reduce access latency and energy consumption, existing approaches have not addressed the challenges posed by systems with many narrow banks, nor have they provided comprehensive evaluation across multiple performance metrics. In this work, we propose a scalable, stride-based bank prediction mechanism that leverages global history to capture correlations in program flow, enabling proactive routing and arbitration decisions for each memory access. This reduces control latency and significantly improves overall system performance. Our unified approach is evaluated using a diverse set of benchmarks and a comprehensive suite of metrics. Experimental results demonstrate that, with a moderate storage budget of 7 KiB per PE, our method achieves a bank prediction accuracy of 94.5% in a 64-bank TCDM configuration.