Programming modern Multi-Processor Systems-on-Chip (MPSoCs) is a complex problem. To address it, academic compilers and programming flows exist that use internal hardware models and simulations to guide the automatic search for an efficient implementation. For the search to be effective, models need to be accurate to guide the search in the right direction and fast to allow for exploration of the large design space that comes with modern architectures. However, academic flows rarely evaluate the accuracy of their models against real hardware. In this paper, we introduce a high-level analytical Network-on-Chip (NoC) model, amenable for integration in MPSoC compilation flows, and validate it against actual hardware. On a trace-driven discrete event simulation, we show potential for a simulation speedup of an order of magnitude compared to a state-of-the-art SystemC model. We show that the model is accurate in low network congestion regimes, using 2, 500 randomly-generated applications. In the case study, our model is within 1% relative error more than 88% of the time, and within 5% more than 99% of the time. Finally, we also stress the model to determine a suitable operational range.