The evolution of communication systems has been the strongest motivation of the rapid improvement of data converters in recent years. In optical communications, utilizing spectrally-efficient modulation schemes was the main key to meet the demand of higher bit rates. This, however, required digital-to-analog converters (DACs) with 5-8 bit resolution at a sampling rate of tens of Gigahertz. In the frame of this work an attempt has been made to address this challenge. After a brief overview of current-steering DAC architectures, the static and dynamic sources of error are mentioned in chapter 2. At medium resolutions, achieving the required static performance is not a critical task in recent silicon technology nodes. On the other hand, the dynamic DAC performance at very high speeds is a different story. In chapter 3, we investigate the impact of the dynamic output impedance and the time response of current switches as decisive factors in understanding DAC high-frequency behaviour. It is shown that a DAC in a bipolar technology can potentially provide two more resolution bits compared to an equivalent CMOS design. To improve the characteristics of a current switch cell as the main bottleneck in designing current-steering DACs, a modified circuit is proposed in chapter 4. Its static and dynamic characteristics are examined and compared with those of a conventional design. A design strategy for better matching of rise (fall) times of different cells is presented. The input capacitor of the presented cell can be lower than that of a cascode differential pair. At the same time, the rise (fall) time mismatch are decreased by factor of two for a targeted 6-bit DAC. Based on this current switch, the 6-bit fully binary DAC with 28 GSps in a SiGe 0.25 μm technology is demonstrated. The measurement results show suitable functionality of this component in a recent 100 Gbps optical transmitter. This design has the best figure-of-merit of binary DACs in a silicon-based technology. Chapter 5 presents a way of generating synchronous bit streams to test a DAC at its full speed. The proposed system is composed of several multiplexers with built-in memory cells. Those multiplexers have to be synchronized by a resettable and also adjustable clock signal. Using a hierarchical top-down method, all the blocks and sub-blocks of the complete system are explained. The measurements of the memory-multiplexer chip as well as clock generator chip are presented. The implemented system in a SiGe 0.25 μm technology is capable of supplying the needed bit stream at 28 GSps.