In this book chapter the authors show device metric predictions as determined by device simulations and present experimental demonstrator results in terms of fabrication and electrical characterization, respectively. Measurements and simulations show that in comparison to Si RFETs, the supply voltage can be reduced by a factor of 2 and dynamic power consumption can be ~4 times lower compared to silicon-based RFETs. In addition, on-currents can be boosted by up to a factor of 10 without degradation of capacitances, bringing a benefit in the intrinsic delay. Performance and power consumption metrics were extracted for different device geometries and benchmarked with modern conventional devices. The authors show that scaled Ge RFETs are competitive compared to modern low standby and low operating power technologies. The performance boosting at the device level combined with the circuit capabilities of RFETs holds the promise of enabling new circuit applications.