Ge_1−xSn_x and Si_1−x−yGe_ySn_x alloys are promising materials for future nanoelectronic applications owing to their high carrier mobilities and CMOS compatibility. However, ternary Si_1−x−yGe_ySn_x transistors have only theoretically been discussed, and there are only a few reports on lateral n-type Ge_1−xSn_x transistors to benchmark their material performance. The low equilibrium solid solubility of Sn in Si_1−xGe_x (less than 1 at%) requires device fabrication processes at temperatures below the growth temperature of Si_1−x−yGe_ySn_x (x > equilibrium solubility) or at non-equilibrium conditions. Therefore, Si-based processes need to be adjusted according to the materials requirements. A relatively easy-to-fabricate device concept are junctionless field effect transistors, which operate as a gated resistor. In this work, we use Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 grown on silicon-on-insulator substrates to fabricate and characterize lateral n-type Ge_1−xSn_x and Si_yGe_1−x−ySn_x junctionless field effect transistors. The transistors were structurally characterized by top-view scanning electron microscopy and cross-sectional transmission electron microscopy. Electrical characterizations by transfer characteristics show the first working n-type Ge_1−xSn_x and Si_1−x−yGe_ySn_x hetero-nanowire transistors, achieving on/off-current ratios of up to eight orders of magnitude.