Exploring RISC-V Instruction-Level Optimization Through Macro-Operation Fusion for TensorFlow-based Models

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Abstract

Macro-operation fusion represents an advanced approach to optimizing instruction streams with the goal of enhancing processor efficiency, offering potential benefits for compute-intensive domains including deep learning and large language models. This work presents a software-based framework designed to systematically explore instruction fusion strategies targeting the RISC-V ISA for TensorFlow-based models. The framework combines model transformation, dynamic instruction trace analysis, and fusion simulation to identify and evaluate both established and novel fusion idioms targeting integer and floating-point operations. Evaluation across a diverse set of benchmarks, spanning classical computational tasks and modern deep learning workloads, demonstrates that the proposed fusion techniques effectively fuse, on average, 30% of dynamic instructions in deep learning models, and over 60% fusion in large language models such as GPT-2. These results provide valuable insights into the trade-offs between software-driven optimization and necessary hardware extensions, informing future RISC-V microarchitecture and compiler design aimed at maximizing instruction-level parallelism.

Details

OriginalspracheEnglisch
Titel2025 IEEE 38th International System-on-Chip Conference (SOCC)
Redakteure/-innenDanella Zhao, Klaus Hofmann
Seiten1-6
Seitenumfang6
ISBN (elektronisch)979-8-3315-9478-7
PublikationsstatusVeröffentlicht - 2025
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE International SOC Conference
ISSN2164-1676

Externe IDs

ORCID /0000-0003-2571-8441/work/203808963
Mendeley 0e728ee8-f939-373a-9d3d-a279fc20d065
unpaywall 10.1109/socc66126.2025.11235386
Scopus 105029599518

Schlagworte

Schlagwörter

  • Instruction Fusion, Instruction-Level Parallelism, Macro-operation Fusion, RISC-V