Energy Efficiency Features of the Intel Alder Lake Architecture

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung


Intel's first heterogeneous processor, Alder Lake, combines two different core architectures from the Core and Atom families: Golden Cove and Gracemont, respectively. While the heterogeneity of this chip can improve performance and energy efficiency, it also increases the complexity of scheduling decisions and power saving mechanisms. In this paper, we analyze performance and energy characteristics of an Alder Lake system and describe effects of power saving mechanisms.We evaluate the factors that influence the time required to switch core and uncore frequencies and waking cores from idle states. In addition, we assess the efficiency of the two core architectures across various workloads.We show that in states with low power consumption, RAPL energy measurements are inaccurate, and actual (externally measured) power consumption also exhibits peculiar patterns. Through experiments, we also examine the newly introduced user space idle states, and the novel telemetry capability. This information can be used by other researchers to design efficient software and further experiments, and explain measured performance on heterogeneous Intel processors.


TitelICPE 2024 - Proceedings of the 15th ACM/SPEC International Conference on Performance Engineering
Herausgeber (Verlag)Association for Computing Machinery
ISBN (elektronisch)979-8-4007-0444-4
PublikationsstatusVeröffentlicht - 7 Mai 2024


Titel2024 ACM/SPEC International Conference on Performance Engineering
Dauer7 - 11 Mai 2024
BekanntheitsgradInternationale Veranstaltung
OrtDepartment of Computing, Imperial College
LandGroßbritannien/Vereinigtes Königreich

Externe IDs

dblp conf/wosp/SchoneVHI24
unpaywall 10.1145/3629526.3645040
ORCID /0000-0002-8491-770X/work/159605027
ORCID /0000-0002-5437-3887/work/159606472
ORCID /0000-0002-2730-0308/work/159607938
Scopus 85193779497


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  • DVFS, energy efficiency, idle state, Intel, power management, RAPL