Enabling MPSoC design space exploration on FPGAs

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Ahsan Shabbir - , Eindhoven University of Technology (Autor:in)
  • Akash Kumar - , Eindhoven University of Technology (Autor:in)
  • Bart Mesman - , Eindhoven University of Technology (Autor:in)
  • Henk Corporaal - , Eindhoven University of Technology (Autor:in)

Abstract

Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. These multiprocessors are increasingly becoming heterogeneous for reasons of cost and power. Design space exploration (DSE) of application mapping becomes a major design decision in such systems. The time spent in DSE becomes even greater with multiple applications executing concurrently. Methods have been proposed to automate generation of multiprocessor designs and prototype them on FPGAs. However, only few are able to support heterogeneous platforms. This is because heterogeneous processors require different types of inter-processor communication interfaces. So when we choose a different processor for a particular task, the communication infrastructure of the processor also has to change. In this paper, we present a module that integrates in a multiprocessor design generation flow and allows heterogeneous platform generation. This module is area efficient and fast. The DSE shows that up to 31% FPGA area can be saved when heterogeneous design is used as compared to a homogeneous platform. Moreover, the performance of the application also improves significantly.

Details

OriginalspracheEnglisch
TitelCommunications in Computer and Information Science
Redakteure/-innenD.M. Akbar Hussain, Abdul Qadeer Khan Rajput, Bhawani Shankar Chowdhry, Quintin Gee
Seiten412-421
Seitenumfang10
PublikationsstatusVeröffentlicht - 2009
Peer-Review-StatusJa
Extern publiziertJa

Publikationsreihe

ReiheCommunications in Computer and Information Science
Band20
ISSN1865-0929

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • FIFO, FPGAs, FSL, MPSoC