The hybrid bonding is well established at wafer level and a very promising technology for fine pitch stacking with through-silicon-via interconnect without solder capped micro bumps. The elimination of solder enables smaller bonding pitches and smaller interconnect sizes. One major challenge of the hybrid bonding technology is the preparation of a clean Cu/SiCh surface with a dedicated Cu recess. Wafer singulation and handling contaminates the die surface and leads to a more complex process flow. For setup and processing of test samples at Fraunhofer IZM ASSID conventional commercially available semiconductor manufacturing equipment was utilized. A test vehicle was designed with a die size of 9,5 mm x 10 mm and a bond pad of 4 um at a pitch of 10 um. The chips were bonded to a coupon of 9 x 5 chips with a chip size of 10 mm x 10 mm. To protect the wafer surface during the singulation process a commercially available protection layer was used. To verify the successful surface preparation the wafer roughness was analyzed using an AFM (atomic force microscope) before and after the protection layer was applied and respectively removed. The stealth dicing singulation method was selected due to its lower particle contamination compared to blade dicing. For the surface activation prior to direct bonding different methods were used. The die placement was performed using a Panasonic Flip Chip Bonder FCB3 (alignment accuracy ±3μm/3sigma). With some modification to the bonding process flow a very good alignment accuracy could be achieved. The alignment check with the IR microscope showed a good placement accuracy as well as bond performance which could be confirmed by electrical testing. The process parameter were defined in advance based on simulation results. The recess in the hybrid surface post CMP process and the copper pad thickness affected the bonding and annealing parameter of the samples.