This thesis addresses basic scientific research in the field of transmitter front-end circuits for electro-optical data communication. First, the theoretical fundamentals are presented and analyzed. Based on the theoretical considerations, conceptual circuit designs are studied. Finally, in order to prove the described concepts, the circuits were experimentally characterized and subsequently compared to other works in the literature. The analysis covers key theoretical aspects regarding transmitter front-end circuits. It starts from the basic physical effects inside a transistor and ends with the design of high-swing modulator drivers. Furthermore, it comprises the fundamentals of optical modulators as well as the integration of the electrical driver with the modulator. First, the concept of a basic monolithically integrated transmitter consisting of a Mach-Zehnder modulator (MZM) and an electrical driver is presented. The circuit reaches a bit-error-free data rate of 37 Gb/s, which is a record among other monolithically integrated transmitters reported in the literature. It was shown that by employing a high-swing driver, high extinction ratios (ER) can be achieved (namely 8.4 dB at 25 Gb/s and 7.6 dB at 35 Gb/s) while using short-length phase shifters (2 mm of length). It was therefore proved that one of the main drawbacks of the MZM-based transmitters, namely their large chip area, can be mitigated by using high-swing drivers, however without sacrificing the ER. Next, an improved modulator driver design is investigated, the focus of the study being the linearity. In addition to a high peak-to-peak differential output voltage swing of 7.2 Vpp,d, the driver achieves record-low total harmonic distortion (THD) values of 1% (at 1 GHz, for the output swing of 6.5 Vpp,d) and 1.7% (at 1 GHz, for the output swing of 7 Vpp,d). Moreover, the driver reaches a bandwidth of 61.2 GHz and shows a high power efficiency when relating its DC power consumption to its output voltage swing. The achievement of a high linearity and bandwidth without an increased power consumption is due to the fact that the bias currents of the emitter-follower (EF) stages are provided by means of resistors instead of the conventional current sources. The two approaches were first analyzed mathematically and subsequently compared by means of circuit simulations. It was shown that the proposed approach for the realization of the EFs – i.e. by means of resistors – allows a reduction of the DC power consumption by 19% compared to the current-source approach for an equivalent performance in terms of linearity and bandwidth. Finally, a modulator driver concept suitable for higher-order modulation formats is studied, namely the 8-level pulse amplitude modulation (PAM-8). The circuit was realized as a 3-bit digital-to-analog converter (DAC), thus being able to yield 8-level output signals. Moreover, the circuit is able to function as a PAM-4 driver as well, thanks to the tunable tail currents of the DAC core. It achieves a symbol rate of 50 Gbaud, which corresponds to a bit rate of 150 Gb/s for the PAM-8 modulation and 100 Gb/s for PAM-4. The study showed that a modulator driver can be realized that is able to switch between different modulation formats (namely PAM-8 and PAM-4), without requiring extra power or additional circuit parts. Moreover, the use of on-chip single-to-differential converters (SDCs) targets the relaxation of the requirements on the stages that precede the driver. Finally, relating its DC power consumption (590 mW, including the SDCs) to its output voltage swing (4 Vpp,d), the driver shows one of the highest power efficiencies among PAM modulator drivers in the literature.