The field of computer vision is continuously increasing and becoming more complex and power demanding. Using feature detection and description allows a fast object detection without needing big databases. FPGAs are predestined for different requirements, like real-time and power constraints, which are important in many application areas. This work proposes a new pattern recognition algorithm, based on an improved Accelerated KAZE (AKAZE) detector and Fast Retina Keypoint (FREAK) descriptor. Our software implementation increased the repeatability in comparison to the original algorithm using optimized configurations. The percentage of correct matching features between two images (repeatability) increased from 85.7% to 91.4%, while the computation time decreases from 70.3ms to 24.9ms. Furthermore, we present an efficient FPGA implementation of the FREAK descriptor. The accelerator processes 2048 features at 73.4 frames per second; achieving a repeatability of 90.9%, while being optimized for resource utilization and memory bandwidth consumption. Additionally, we show an efficient Integral Image implementation that processes four image pixels per clock cycle at a high frequency (204 MHz on xc7z020clg484-1) consuming minimum resources.