Dynamic voltage and frequency scaling for neuromorphic many-core systems
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Beitragende
Abstract
We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; the effectiveness of the power management technique is demonstrated using a standard benchmark from the application domain. The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark - the synfire chain - we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.
Details
Originalsprache | Englisch |
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Titel | 2017 IEEE International Symposium on Circuits and Systems (ISCAS) |
Erscheinungsort | Baltimore |
Herausgeber (Verlag) | IEEE Xplore |
ISBN (elektronisch) | 978-1-4673-6853-7 |
ISBN (Print) | 978-1-5090-1427-9 |
Publikationsstatus | Veröffentlicht - 25 Sept. 2017 |
Peer-Review-Status | Ja |
Publikationsreihe
Reihe | IEEE International Symposium on Circuits and Systems (ISCAS) |
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ISSN | 0271-4302 |
Konferenz
Titel | IEEE International Symposium on Circuits and Systems 2017 |
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Kurztitel | ISCAS 2017 |
Veranstaltungsnummer | 50 |
Dauer | 28 - 31 Mai 2017 |
Stadt | Baltimore |
Land | USA/Vereinigte Staaten |
Externe IDs
ORCID | /0000-0002-6286-5064/work/142240637 |
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Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- DVFS, MPSoC, neuromorphic computing, power management, SpiNNaker2, synfire chain