Dynamic off-state TDDB of ultra short channel HKMG nFETS and its implications on CMOS logic reliability

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • S. Kupke - , Technische Universität Dresden (Autor:in)
  • S. Knebel - , Professur für Turbomaschinen und Flugantriebe, NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • S. Rahman - , Technische Universität Dresden (Autor:in)
  • S. Slesazeck - , Technische Universität Dresden (Autor:in)
  • T. Mikolajick - , Professur für Nanoelektronik, NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • R. Agaiby - , Global Foundries, Inc. (Autor:in)
  • M. Trentzsch - , Global Foundries, Inc. (Autor:in)

Abstract

The impact of DC off-state and AC gate + off-state stress on the time dependent dielectric breakdown (TDDB) of ultra-short channel high-k/metal gate (HKMG) nMOSFETs was investigated. Under high DC off-state (drain) bias, the dielectric wear out was found to be caused by hot hole injection at the drain side. The breakdown time scaled with the gate length in accordance with a higher impact ionization rate by an increased subthreshold leakage current for shorter channels. At identical bias, drain-only stress results in a less severe degradation in comparison to gate-only stress. However, the combination of alternating gate and off-state stress results in a lower lifetime compared to DC and AC gate-only stress. The AC gate + off-state pattern exhibits a similar degradation behavior as bipolar AC stress, attributed to continuous charge trapping and detrapping in the gate oxide. The TDDB failure distribution did not obey the Poisson area scaling assuming randomly generated defects. The spatial asymmetric breakdown localized at the drain edge could be described applying a more general negative binominal yield model.

Details

OriginalspracheEnglisch
Titel2014 IEEE International Reliability Physics Symposium, IRPS 2014
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seiten5B.1.1-5B.1.6
ISBN (elektronisch)978-1-4799-3317-4
ISBN (Print)9781479933167
PublikationsstatusVeröffentlicht - 2014
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE International Reliability Physics Symposium Proceedings
ISSN1541-7026

Konferenz

Titel52nd IEEE International Reliability Physics Symposium, IRPS 2014
Dauer1 - 5 Juni 2014
StadtWaikoloa, HI
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0003-3814-0378/work/142256299

Schlagworte

ASJC Scopus Sachgebiete

Schlagwörter

  • BTI, CMOS, logic circuits, off-state, reliability, TDDB