DownShift: Tuning Shift Reduction with Reliability for Racetrack Memories

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung



Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate shift operations in RTMs, required for data access, incur performance penalties and can induce position errors. These factors can hinder their applicability in replacing low-latency, reliable on-chip memories. Intelligent placement of memory objects in RTMs can significantly reduce the number of shifts per memory access with little to no hardware overhead. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. Additionally, the impact of these shift optimization techniques on RTM reliability has been insufficiently investigated. We propose DownShift, a generalized data placement mechanism that improves upon prior approaches by taking into account (1) the timing and liveliness information of memory objects and (2) the underlying memory architecture, including required shifting fault tolerance. Thus, we also propose a collaboratively designed new shift alignment reliability technique called GROGU. GROGU leverages the reduced shift window made possible through DownShift allowing improved reliability, area, and energy compared to the state-of-the-art reliability approaches. DownShift reduces the number of shifts, runtime, and energy consumption by 3.24×, 47.6%, and 70.8% compared to the state-of-the-art. GROGU consumes 2.2× less area and 1.3× less energy while providing 16.8× improvement in shift fault tolerance compared to the leading reliability approach for a latency degradation of only 3.2%.


Seiten (von - bis)2585-2599
FachzeitschriftIEEE Transactions on Computers
PublikationsstatusVeröffentlicht - 1 Sept. 2023

Externe IDs

ORCID /0000-0002-5007-445X/work/160049126


Ziele für nachhaltige Entwicklung


  • Data placement, domain wall memory, misalignment fault tolerance, racetrack memory, shift minimization