Dynamic Partial Reconfiguration (DPR) has become increasingly attractive for Field Programmable Gate Array (FPGA) platforms, as it allows to use the available space on the FPGA more efficiently. This results in a more complicated mapping process for dynamically reconfigurable platforms, but also enables application deployments that were infeasible before, which should be considered for the Design Space Exploration (DSE) of Network-On-Chip (NoC) architectures. Therefore, this work presents a DSE framework, which allows to optimize the microarchitecture of a NoC router based on an abstract application and platform description. The underlying models thereby allow the incorporation of DPR, which is why a methodology for mapping application task graphs to dynamically reconfigurable platforms is proposed. By utilizing modern Multiobjective Evolutionary Algorithm (MOEA), the large design space of the NoC router is efficiently explored without requiring preliminary constraints to decision variables. Concrete NoC architectures are evaluated with the help of the highly parameterizable PANACA platform. Additionally, tools for visualizing and analyzing the found results are provided.