C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory
Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung
Beitragende
Abstract
Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.
Details
Originalsprache | Englisch |
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Seiten (von - bis) | 1595-1605 |
Seitenumfang | 11 |
Fachzeitschrift | IEEE Transactions on Circuits and Systems : a publication of the IEEE Circuits and Systems Society. 1, Regular Papers |
Jahrgang | 69 |
Ausgabenummer | 4 |
Publikationsstatus | Veröffentlicht - 10 Jan. 2022 |
Peer-Review-Status | Ja |
Externe IDs
Scopus | 85123343053 |
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WOS | 000742687600001 |
Mendeley | 80501e7f-7851-3e21-b4a2-e49ac35dc929 |
dblp | journals/tcasI/DahanBSMK22 |
Schlagworte
DFG-Fachsystematik nach Fachkollegium
ASJC Scopus Sachgebiete
Schlagwörter
- Array architecture, Emerging memory technology, Ferroelectric field effect transistor (FeFET), Memory, Voltage measurement, memory, Switches, Microprocessors, Logic gates, Writing, Transistors, FeFETs, emerging memory technology, array architecture