CADSE: Communication aware design space exploration for efficient run-time MPSoC management

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Beitragende

  • Amit Kumar Singh - , National University of Singapore, Nanyang Technological University (Autor:in)
  • Akash Kumar - , National University of Singapore (Autor:in)
  • Jigang Wu - , Tiangong University (Autor:in)
  • Thambipillai Srikanthan - , Nanyang Technological University (Autor:in)

Abstract

Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip (MPSoC). Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisfy their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources' status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration (CADSE) techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.

Details

OriginalspracheEnglisch
Seiten (von - bis)416-430
Seitenumfang15
FachzeitschriftFrontiers of Computer Science
Jahrgang7
Ausgabenummer3
PublikationsstatusVeröffentlicht - Juni 2013
Peer-Review-StatusJa
Extern publiziertJa

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • design space exploration, multiprocessor systems-on-chip, run-time mapping, synchronous dataflow graphs, throughput