In artificial neural networks, the “synaptic weights” connecting the neurons are adjusted during the training. Beyond silicon, functionalizing the back-end-of-line (BEOL) of CMOS circuits with novel materials is a key enabler for deploying neural network accelerators. The hardware implementation of the synaptic weights requires linear and reprogrammable resistive elements. In ferroelectric tunnel junctions, the resistance is programmed by controlling the configuration of the ferroelectric domains with electrical pulses. From ferroelectric HfZrO₄ to HfO₂–ZrO₂ nanolaminates (NL), the crystallization temperature lowers below the upper limit of 400 °C required for CMOS BEOL. The device footprint is reduced, and the maximum-to-minimum conductance ratio increases from 7 to 32. Operated with pulses in the ultra-fast (20 ns) and biological (500 µs) timescales, the synaptic plasticity exhibits several regimes. Dynamic hysteresis mode characterization after up to 10¹¹ switching cycles indicates the coexistence of ferroelectric and non-ferroelectric effects such as defect rearrangement. Temperature-dependent transport measurements in the Ohmic (linear) regime support these conclusions. Multi-level resistive switching is achieved in HfO₂–ZrO₂ NL co-integrated to CMOS in the BEOL. 1T-1R operation is demonstrated, paving the way for hardware implementation of synaptic weights for in-memory neuromorphic computing.