Backend for virtual platforms with hardware scheduler in the MAPS framework

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung


  • Jeronimo Castrillon - , RWTH Aachen University (Autor:in)
  • Aamer Shah - , RWTH Aachen University (Autor:in)
  • Luis Gabriel Murillo - , RWTH Aachen University (Autor:in)
  • Rainer Leupers - , RWTH Aachen University (Autor:in)
  • Gerd Ascheid - , RWTH Aachen University (Autor:in)


Advances in process integration, the power wall and end-user application demands have made Multi-Processor Systems on Chip (MPSoCs) a reality. In mobile embedded devices, these systems are heterogeneous in order to cope with stringent real time and energy constraints, which makes them difficult to program, debug and verify. Therefore, a lot of research in industry and academia has focused on providing solutions to this MPSoC programming problem. In this paper we study and extend one of such frameworks, namely, the MPSoC Application Programming Studio (MAPS) [1]. We analyze MAPS retargetability by adding a new backend for a heterogeneous MPSoC with the OSIP hardware scheduler [2]. The new backend exports high level debugging information that is included in an environment for application debugging based on virtual platforms. The extensions are demonstrated on a heterogeneous virtual platform running the JPEG application.


Titel2011 IEEE 2nd Latin American Symposium on Circuits and Systems, LASCAS 2011 - Conference Proceedings
PublikationsstatusVeröffentlicht - 2011
Extern publiziertJa


Titel2011 IEEE 2nd Latin American Symposium on Circuits and Systems, LASCAS 2011
Dauer23 - 25 Februar 2011

Externe IDs

ORCID /0000-0002-5007-445X/work/141545601


Forschungsprofillinien der TU Dresden


  • code generation, hardware scheduler, MPSoC debugging, MPSoC programming, virtual platforms