Backend for virtual platforms with hardware scheduler in the MAPS framework
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
Advances in process integration, the power wall and end-user application demands have made Multi-Processor Systems on Chip (MPSoCs) a reality. In mobile embedded devices, these systems are heterogeneous in order to cope with stringent real time and energy constraints, which makes them difficult to program, debug and verify. Therefore, a lot of research in industry and academia has focused on providing solutions to this MPSoC programming problem. In this paper we study and extend one of such frameworks, namely, the MPSoC Application Programming Studio (MAPS) [1]. We analyze MAPS retargetability by adding a new backend for a heterogeneous MPSoC with the OSIP hardware scheduler [2]. The new backend exports high level debugging information that is included in an environment for application debugging based on virtual platforms. The extensions are demonstrated on a heterogeneous virtual platform running the JPEG application.
Details
Originalsprache | Englisch |
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Titel | 2011 IEEE 2nd Latin American Symposium on Circuits and Systems, LASCAS 2011 - Conference Proceedings |
Publikationsstatus | Veröffentlicht - 2011 |
Peer-Review-Status | Ja |
Extern publiziert | Ja |
Konferenz
Titel | 2011 IEEE 2nd Latin American Symposium on Circuits and Systems, LASCAS 2011 |
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Dauer | 23 - 25 Februar 2011 |
Stadt | Bogota |
Land | Kolumbien |
Externe IDs
ORCID | /0000-0002-5007-445X/work/141545601 |
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Schlagworte
Forschungsprofillinien der TU Dresden
ASJC Scopus Sachgebiete
Schlagwörter
- code generation, hardware scheduler, MPSoC debugging, MPSoC programming, virtual platforms