Innovative material and processing concepts are needed to further enhance the performance of complementary metal-oxide-semiconductor (CMOS) transistors-based circuits as the scaling limits are being reached. To supplement that, we report on the development of an atomic layer etching (ALE) process to fabricate small and smooth nanowires using a conventional dry etching tool. Firstly, a negative tone resist (hydrogen silsesquioxane) is spin-coated on Silicon Germanium-on-insulator (SiGeOI) samples and electron beam lithography is performed to create nanopatterns. These patterns act as an etch mask and are transferred into the SiGeOI layer using an inductively-coupled plasma reactive ion etching (ICP-RIE) process. Subsequently, an SF6 and Ar+ based ALE process is employed to smoothen the nanowires and reduce their widths. SF6 modifies the surface of the samples, while in the next step Ar+ removes the modified surface. To investigate the effect of this process on the nanowire width, several ALE cycles are performed. The etched features are inspected using scanning electron microscopy. With the increasing number of ALE cycles, a reduction in the width is observed. An etch per cycle of 1.1 Å is obtained.