Future chips are anticipated to feature hundreds of on-die resources, but a significant portion of silicon area in these chips will be powered-off or “dark”. As a result, only a limited number of cores of future processors can be powered on simultaneously. In this paper, a novel NoC architecture is proposed, called Dark Silicon Synchronous-Asynchronous (DSSA) NoC, that offer a promising solution from the latency perspective in consideration to the number of hops from source to destination. In this design two layers of architecturally analogous synchronous and asynchronous TDM routers are integrated, leveraging the extra transistors available due to dark silicon for a hard real-time multiprocessor platform. At a given time, at most, only one of the network layers is illuminated while the other is dark. Layer selection performed at the granularity of router port with applied power gating technique uniquely in a source routed TDM router. To verify the design, a4×4 bitorus synchronous, asynchronous and DSSA NoCs are implemented in 90-nm CMOS technology and the results are compared in the fields of area, speed, latency and power consumption, which shows improved message latency by DSSA NoC. The results further show the effects of the power gating technique to the TDM NoC, which offers up to 50% power savings in comparison to the conventional synchronous and asynchronous TDM NoCs. This illustrates DSSA as an improved latency NoC solution in future dark silicon chips.