An Energy Efficiency Feature Survey of the Intel Haswell Processor.
Publikation: Beitrag zu Konferenzen › Paper › Beigetragen › Begutachtung
Beitragende
Abstract
The recently introduced Intel Xeon E5-1600 v3 and E5-2600 v3 series processors -- codenamed Haswell-EP -- implement major changes compared to their predecessors. Among these changes are integrated voltage regulators that enable individual voltages and frequencies for every core. In this paper we analyze a number of consequences of this development that are of utmost importance for energy efficiency optimization strategies such as dynamic voltage and frequency scaling (DVFS) and dynamic concurrency throttling (DCT). This includes the enhanced RAPL implementation and its improved accuracy as it moves from modeling to actual measurement. Another fundamental change is that every clock speed above AVX frequency -- including nominal frequency -- is opportunistic and unreliable, which vastly decreases performance predictability with potential effects on scalability. Moreover, we characterize significantly changed p-state transition behavior, and determine crucial memory performance data.
Details
Originalsprache | Englisch |
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Seiten | 896-904 |
Publikationsstatus | Veröffentlicht - 2015 |
Peer-Review-Status | Ja |
Workshop
Titel | 2015 IEEE International Symposium on Parallel and Distributed Processing Workshops - HPPAC—High-Performance, Power-Aware Computing |
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Kurztitel | IPDPSWS-HPPAC 2015 |
Dauer | 25 - 29 Mai 2015 |
Webseite | |
Bekanntheitsgrad | Internationale Veranstaltung |
Stadt | Hyderabad |
Land | Indien |
Externe IDs
Scopus | 84962251153 |
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ORCID | /0000-0002-8491-770X/work/141543292 |
ORCID | /0000-0001-6967-8707/work/141544818 |
ORCID | /0009-0003-0666-4166/work/151475596 |
ORCID | /0000-0002-5437-3887/work/154740509 |