Acceleration of 2D SAR Imaging on FPGA by Reducing off-chip Memory Accesses

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung



Terahertz (THz) Synthetic Aperture Radar (SAR) is a powerful and emerging imaging technique that is capable of providing high-resolution images in the sub-millimeter range. One of the primary applications is the environment mapping and profiling with unmanned aerial vehicle (UAV) based THz SAR. Field-Programmable Gate Arrays (FPGAs) have demonstrated promising results in accelerating signal processing applications. FPGAs are able to meet the real-time requirements for environment mapping and also have the advantage of low power consumption. In this paper, a memory-optimized embedded platform is proposed for 2D SAR imaging. Since off-chip memory access latency and energy consumption are dominant in 2D SAR, this work aims to reduce off-chip memory accesses and manage on-chip memory usage to accelerate 2D SAR. The proposed 2D SAR is implemented and evaluated on a Xilinx Zynq MPSoC FPGA board. The experimental results show 86.2× improvement in term of execution time compared to the MATLAB model running on a single CPU (intel 7-4790 @3.7 GHz).


Titel2023 6th International Workshop on Mobile Terahertz Systems, IWMTS 2023
Herausgeber (Verlag)IEEE
ISBN (elektronisch)9798350321159
PublikationsstatusVeröffentlicht - 3 Juli 2023


ReiheInternational Workshop on Mobile Terahertz Systems (IWMTS)

Externe IDs

unpaywall 10.1109/iwmts58186.2023.10207859
ORCID /0000-0002-8019-7936/work/142238036
ORCID /0000-0003-2571-8441/work/142240593
Scopus 85169414339
Mendeley 3b0afbee-c8df-3cad-ab8a-fed4b4ae087f


Forschungsprofillinien der TU Dresden

Ziele für nachhaltige Entwicklung


  • Field Programmable Gate Arrays (FPGA), THz imaging, radar imaging, real-time processing