Machine learning algorithms are seeing an increase in data sparsity due to optimization techniques and model compression methods. However, traditional accelerators underperform in sparse workloads due to wasted computations on zero-elements. Therefore, specialized architectures are needed to accelerate sparse computations, with a close-coupling to general-purpose processors to leverage algorithm-level optimizations. This work proposes a RISC-V coprocessor to accelerate structured sparse-dense matrix multiplications with a scalable tile-based architecture that can directly be controlled through the RISC-V core using a custom instruction set. Prototyping this design on an AMD/Xilinx ZCU104 shows a lightweight design consuming less than 60 mW of dynamic power, and an analysis of its performance shows 85-100X speedup compared to CPU.