A resource optimized SoC kit for FPGAs
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. A key component of such configurable system on a chip (CSoC) is the processor core. Available and usable cores are either 32 or 8 bit wide. Thus, there is a gap between these two extremes, which we want to fill with our SoC kit. In this contribution we elaborate on our SoC kit and its components and compare it to other SoC design environments.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL |
| Seiten | 761-764 |
| Seitenumfang | 4 |
| ISBN (elektronisch) | 978-1-4244-1060-6 |
| Publikationsstatus | Veröffentlicht - 2007 |
| Peer-Review-Status | Ja |
Konferenz
| Titel | 17th International Conference on Field Programmable Logic and Applications |
|---|---|
| Kurztitel | FPL 2007 |
| Veranstaltungsnummer | 17 |
| Dauer | 27 - 29 August 2007 |
| Stadt | Amsterdam |
| Land | Niederlande |