This paper presents the design and measurement results of a 2.5 GS/s 7 bit successive approximation register (SAR) analog-to-digital converter (ADC) with real-time data output using the JESD204B protocol. It is implemented as quadruple time interleaved ADC in a 22 nm fully-depleted silicon-on-insulator technology and consumes 43mW overall, while the analog frontend (ADC cores and interleaver) consumes only 7.8mW. Up to the Nyquist frequency, the effective number of bits is larger than 6.1 bit leading to a Walden Figure-of-Merit of 45 fJ/conv.-step and a Schreier Figure-of-Merit of 150.5 dB. Integral and differential nonlinearity are both well below 0.5 LSB for all measurement scenarios.