The continued scaling of CMOS semiconductor technology, together with the corresponding reduction of operating voltages, pose serious challenges for SRAM arrays regarding susceptibility to parameter variations, reduction of stability margins and reliability of read and write operations. One approach, alternative to various noise margin definitions, is to characterize the robustness of SRAM cells via the computation of stability boundaries, also referred to as separatrices. These curves define threshold voltages producing a flip in the logical state of an SRAM cell, which may lead to data loss due to disturbances, e.g. during read operations. The present work proposes a numerical approach to compute families of parameter-dependent separatrices based on path-following (continuation) methods, exploiting the geometric features of one-dimensional stable manifolds around saddle equilibria. The proposed approach is tested on an SRAM cell whose mathematical description is carried out in detail, based on the EKV (Enz, Krummenacher and Vittoz) equations for MOS transistors. In addition, the present work includes a comprehensive numerical study of the effect of parameter perturbations on separatrices, in a computationally efficient manner.