A 60-GHz radar receiver circuit with a gain-linearity tuning capability is implemented in a 130-nm SiGe BiCMOS technology. The receiver has up to 36 dB conversion gain and a measured single-sideband noise figure of 6 dB. Due to an integrated linearizer circuit, the 1-dB compression point can be tuned from-42 dBm up to-30 dBm, at a gain reduction of only 5.7 dB. The receiver can be operated with an LO signal power as low as-25 dBm due to the integrated driver amplifier. The receiver chip consumes 195 mW of dc power and occupies an area of 1.1 mm2.