A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver
Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung
Beitragende
Abstract
This paper describes the design of an energy-efficient vertical-cavity surface-emitting laser (VCSEL) driver circuit implemented in a 130 nm SiGe BiCMOS technology. The driver features a 3-tap feed-forward equalizer where positive and negative peaks are added to the main signal to compensate for the low-pass characteristic of VCSELs. The circuit is also able to generate asymmetric pre-emphasis to counteract the VCSEL nonlinearity. Bonded to an 18 GHz VCSEL, the driver can reach an error-free (bit error rate < 10-12) optical data rate of 50 Gb/s with an horizontal eye opening better than 0.2 unit interval using a 22 GHz photoreceiver without equalization, retiming, and limiting amplifier at the receiver side. At 48 Gb/s, the horizontal eye opening is 0.5 unit interval. The circuit dissipates only 190 mW from a dual supply of 2.5 and 3.3 V, including the VCSEL power. To the best of the authors' knowledge, this is the fastest common-cathode VCSEL driver with lowest power consumption for data rates higher than 35 Gb/s. Thanks to the active delay line and the application of vertical inductor, the driver is very compact with an active area of only 0.036 mm2 including the inductor.
Details
Originalsprache | Englisch |
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Seiten (von - bis) | 2422-2429 |
Seitenumfang | 8 |
Fachzeitschrift | IEEE Journal of Solid-State Circuits |
Jahrgang | 52 |
Ausgabenummer | 9 |
Publikationsstatus | Veröffentlicht - 2017 |
Peer-Review-Status | Ja |
Externe IDs
Scopus | 85023634984 |
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researchoutputwizard | legacy.publication#82402 |
ORCID | /0000-0002-1851-6828/work/142256723 |
Schlagworte
Forschungsprofillinien der TU Dresden
Schlagwörter
- A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver