A 10.5µW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Marcel Jotschke - , Fraunhofer Institut für Integrierte Schaltungen (Autor:in)
  • Wilmar Carvajal Ossa - , Fraunhofer Institut für Integrierte Schaltungen (Autor:in)
  • Torsten Reich - , Fraunhofer Institut für Integrierte Schaltungen (Autor:in)
  • Christian Mayr - , Professur für Hochparallele VLSI-Systeme und Neuromikroelektronik (Autor:in)

Abstract

Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. The analog frontend (AFE) plays a key role in this context. This paper presents a successive approximation register analog-to-digital converter (SAR ADC) with a switched-capacitor programmable gain switched preamplifier (SCPGSA), as a basic component of an integrated ultra-low power AFE. AFE resolution, sample rate and signal gain are configurable between 6 to 13bit, 1 to 10kS/s and -6 to 12dB, respectively. The circuit draws 10.5µW from a 1.8V standard supply voltage, achieving an effective number of bits of 12.6bit and a Walden figure of merit of 169.1fJ/st. and 30.6fJ/st., computed with and without preamplifier, respectively. The circuit is employed in a modular internet of things sensor node, suitable to be solely powered from microenergy sources (energy harvesters). In order to feed charge-scaling SAR ADC inputs with the sensor voltages, typically a preamplifier stage is implemented, which can create energy overhead of magnitudes larger than the ADC power. This paper presents a duty-cycled preamplifier with programmable gain for SAR ADCs, utilizing switched-capacitor switched-opamp technique in the SCPGSA. No additional buffer circuitry is needed to charge the SAR ADC, and the preamplifier design is relaxed in power constraint. The circuit targets the low-cost internet of things market. Cost efficiency is achieved by technology choice, wide configurability and shortened ASIC design cycles. The latter results from partly generated layout, easing reuse of circuit parts from a different CMOS node. A testchip in a low-cost 180nm silicon-on-insulator technology was fabricated.

Details

OriginalspracheEnglisch
TitelIEEE World Forum on Internet of Things, WF-IoT 2020 - Symposium Proceedings
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seitenumfang6
ISBN (elektronisch)978-1-7281-5503-6
PublikationsstatusVeröffentlicht - Juni 2020
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE World Forum on Internet of Things (WF-IoT)

Konferenz

Titel6th IEEE World Forum on Internet of Things, WF-IoT 2020
Dauer2 - 16 Juni 2020
StadtNew Orleans
LandUSA/Vereinigte Staaten

Externe IDs

Scopus 85095596666