A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias & zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers (IEEE) |
| Seiten | 45-48 |
| Seitenumfang | 4 |
| ISBN (Print) | 978-1-4799-0277-4 |
| Publikationsstatus | Veröffentlicht - 13 Nov. 2013 |
| Peer-Review-Status | Ja |
Konferenz
| Titel | 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
|---|---|
| Dauer | 11 - 13 November 2013 |
| Ort | Singapore |
Externe IDs
| Scopus | 84893559858 |
|---|---|
| ORCID | /0000-0002-4152-1203/work/165453435 |
Schlagworte
Schlagwörter
- Detectors, Pulse width modulation, CMOS integrated circuits, Clocks, Inductors, Logic gates, Voltage control