The escalating demand for energy-efficient embedded systems necessitates innovative approaches to mitigate dynamic power consumption in general-purpose cores. This paper introduces a threshold-based, workload-adaptive clockgating technique for a dual-issue RISC-V core, dynamically disabling the underutilized second-issue datapath to reduce dynamic power consumption. The method employs a threshold-based clock-gating controller that dynamically activates the secondissue pipeline according to the target workload and desired energy/performance trade-offs. By integrating latch- and flip-flop-based clock-gating mechanisms into the open-source VeeR EH1 dual-issue core, coarse-grained control over the secondissue pipeline is achieved, enhancing energy efficiency with minimal impact on computing performance. For prototyping and evaluation, an FPGA implementation targeting AMD/Xilinx FPGA devices, along with CoreMark benchmark evaluation, has been conducted, demonstrating 5% improvement in energy efficiency and a dynamic power savings of up to 15%, making the approach particularly suitable for power-constrained embedded systems.