Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning
Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung
Beitragende
Abstract
This letter presents a scalable technique to reduce the power of the analog input stage in neural recording front-ends in Globalfoundries 22 -nm FDSOI. The back-gate voltages are adapted to reduce the threshold voltage and thus allow supply voltage reduction. This adaption increases PVT stability of subthreshold circuits. A comparison to a conventional delta-sigma ADC is drawn and the minimum power point is measured, resulting in 0.7 - μW/channel at 7.2 - μV input-referred noise. Additionally, the transition to smaller technologies promises low-power consumption in the digital domain, by allowing smaller supply voltage and higher integration density.
Details
Originalsprache | Englisch |
---|---|
Seiten (von - bis) | 145-148 |
Seitenumfang | 4 |
Fachzeitschrift | IEEE Solid-State Circuits Letters |
Jahrgang | 6 |
Publikationsstatus | Veröffentlicht - 2023 |
Peer-Review-Status | Ja |
Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- 1/f-noise, back-gate adaptation, low-noise amplifiers, operational amplifiers, recording